摘要
采用Delta-Sigma结构的调制器可降低锁相环路中小数分频时所产生的量化噪声对系统的影响。通过分析Delta-Sigma工作原理推导其噪声传输函数,得出增加Delta-Sigma调制器的阶数或增加过采用率均能减小量化噪声功率。累加器结构的3阶内插型Delta-Sigma调制器结构简单,可有效降低芯片面积,且内插型结构适合以尽量降低环路噪声为目标的设计。
The effect of quantization noise from fractional frequency division in PLL on system can be minimized if Delta-Sigma modulator is used. By analyzing the principle of Delta-Sigma and derivation of its noise transfer function, it can be shown that the quantization noise can be minimized by increasing the order of Delta-Sigma or by increasing the over-sampling rate. The 3rd order interpolative Delta-Sigma modulator with accumulator is simple in structure and contributes to decreasing chip area. Also, this structure is suitable for decreasin,, loop noise design.
出处
《电子工程师》
2008年第6期43-46,共4页
Electronic Engineer
