高性能数字电视QAM均衡器的VLSI结构设计

Design of a VLSI architecture for a high performance QAM equalizer for HDTV receiver

本文设计了一种适用于高清晰数字电视(HDTV)接收芯片的全数字正交幅度调制器(QAM)的均衡器。该均衡器由前馈滤波器、误差判别电路和系数更新电路以及后馈滤波器构成。该均衡器采用了常模算法(CMA)和判决导引最小均方算法(DD-LMS)相结合的算法。重点给出了均衡器的VLSI实现、两种算法间切换的依据、步长的选择以及抽头系数的确定。同时在电路上采用了逻辑简化、重编码、电路时分复用等简化和优化方法来实现性能、面积和功耗的折衷。

An all-digital QAM equalizer architecture is presented for HDTV receiver chip. This equalizer incorporates forward filter, error judge, coefficient updating and decision-feed back equalizer. This equalizer adopts CMA and DD-LMS algorithm. It emphasizes on realizing the VLSI （ very large scale integrated-circuit ）. the rule between the algorithms, the selection of step and filter＇ s coefficient. At the same time, the circuit attains trade-off among performance, area and power by applying simplicity in logic, re-code technology and other optimization measure.