DVB-S2系统中LDPC编码的FPGA实现

FPGA implementation of LDPC encoder in DVB-S2

分析了DVB-S2中LDPC码的特点,给出了一种面向FPGA的LDPC码编码实现方案,并采用Verilog HDL语言在Virtex 4 xc4vlx60芯片上实现了该编码器的设计,设计采用多个BlockRAM存储校验位,实现了与同一信息位关联的所有校验位的并行处理,提高了编码速度。综合结果表明:该编码器的吞吐量约为49.95 Mbit/s,在占用资源较少的情况下满足了DVB-S2标准的要求。

This paper analyses the characteristics of the LDPC code in DVB-S2, and proposes an encoding architecture for FPGA implemented with Verilog HDL language on the chip of Virtex 4 xc4vlx60. The design method adopts many Block-RAMs to process all the parity bits relating to the same information bit in parallel, thus improving the encoding speed. Synthesis results show that this encoder has a throughput about 49.95 Mbps, which satisfies the demand of DVB-S2 at the cost of low resource occupation.