分组密码IDEA的FPGA实现

Implementation of the IDEA encryption arithmetic based on FPGA

根据IDEA密钥扩展方式和加解密流程,采用FPGA技术,对IDEA的功能模块进行了划分和设计,重点介绍了该文中所设计的关键功能模块的实现方法。给出了Verilog语言编写的实现该算法的关键性源代码。最后,对该IDEA算法加/解密模块进行了较全面的测试及性能分析。理论分析和仿真的结果表明,该模块能够准确实现加密和解密。

IDEA encryption/decryption module is implemented using FPGA. Design of main functional modules is described, which are partitioned based on the key expansion and the encryption/decryption flow of IDEA. Then the main source code written in Verilog HDL language is presented. Finally, the all-round test and analysis to the performance results are given, from both theoretical analysis and simulation show that the module can encrypt and decrypt correctly.