一种高效去块滤波结构设计与VLSI实现

A Novel and Hardware Efficient Deblocking Filter for H.264/AVC

提出一种用于H.264/AVC环路去块效应滤波器设计的VLSI实现结构。通过采用流水数据通路设计提高了去块效应滤波处理的速度。重新组织了滤波顺序以适应流水处理的需要。通过合理设计缓冲机制,在增加少量片内RAM的情况下,提高了外部存储器的吞吐效率和系统的处理性能。试验结果表明,相对已有的实现结构,提出的结构以较少的资源消耗实现了200MH z的处理速度,可满足4路分辨率为1280×720的实时视频处理。

Aim. Comparatively hardware efficient deblocking filter for H. 264/AVC （advanced video coding）is, in our opinion, still not as efficient as is possible. We now present a novel VLSI （very large scale integrated） architecture for the deblocking filter in H. 264/AVC that is better. In the full paper, we explain our VLSI architecture in some detail; in this abstract, we just add some pertinent remarks to listing the three topics of explanation. The first topic is： the algorithm for the deblocking filter in H. 264/ AVC. In this topic, we use the pipelined data path and the re-rranged filtering order to quicken the deblocking speed, as shown in Figs. 2（a） through （c） in the full paper. The second topic is： designing the VLSI architecture for the deblocking filter. In this topic, we designed the implementation flow chart of the VLSI architecture as shown in Fig. 3. The deblocking filter consists of the following core modules： the pipeline edge loop filter module to implement boundary filtering, output data buffering module to buffer the filtered data and then input them into the external SDRAM （synchronized dynamic random access memory） and the improved pipelined 4×4 matrix transposition module to transpose the matrix. We also propose a fully pipelined 4×4 matrix transposition architecture to input and output matrix-transposed data continuously. The third topic is： experimental results and their analysis. In this topic, we use VerilogHDL and Synopsys DC compiler to design and synthesize our architecture and compare the performance of our architecture with those of the architectures in Refs E63 through E83, with the comparison results given in Tables 2 and 3. The analysis of the experimental results presented above shows preliminarily that our architecture raises the external SDRAM throughput rate and easily support 4- channel real-time 1 280×720 resolution video devices when their maximal frequency is 200 MHz.