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基于SOC应用的运算放大器IP核设计 被引量:3

Design of Operational Amplifier IP Core for SOC Application
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摘要 基于SOC应用,采用TSMC0.18μm CMOS工艺,设计实现了一个低电压、高增益的恒跨导轨到轨运算放大器IP核。该运放采用了一倍电流镜跨导恒定方式和新型的共栅频率补偿技术,比传统结构更加简单高效。用Hspice对整个电路进行仿真,在1.8V电源电压、10pF负载电容条件下,其直流开环增益达到103.5dB,相位裕度为60.5度,输入级跨导最大偏差低于3%。 Based on SOC application, a low voltage, high gain rail to rail operational amplifier IP core with constant-transconductance is presented, It will be realized in TSMC 0.18μm CMOS process. The transconductance of input stage is controlled by a method of current mirror and new. common-gate frequency compensation is used. The whole circuit is simulated with 1.8V power supply, 10pF capacitive load in Hspice, it is shown that the amplifier has an open loop gain of 103.5dB, a phase margin of 60.5 degrees and a low transconductor deviation of 3%.
出处 《微计算机信息》 北大核心 2008年第20期167-169,共3页 Control & Automation
基金 国家自然科学基金(60466047) 部委基金资助项目(51408010304DZ0140)
关键词 运算放大器 轨到轨 共栅频率补偿 IP核 operational amplifier Rail to Rail common gate compensation IP core
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参考文献6

  • 1Trung K N, Sang G L. Low-voltage, low-power CMOS operation transconductance amplifier with Rail-to-Rail differential input range [J]. IEEE ISCAS. 2006; 10:1639-1642
  • 2侯卫卫,冯全源.一种高性能单位增益放大器[J].微计算机信息,2007,23(02Z):292-293. 被引量:3
  • 3Juan. M. Carrillo, Francisco J, Duque-carrillo, et al. Constantgm constant-slew-rate high-bandwidth low-voltage Rail-to-Rail CMOS input stage for VLSI cell libraries [J]. IEEE International Symposium on Circuits and Systems, 2003; 38(1): 165-168
  • 4Loikkanen M, Kostamovaara J. Low voltage CMOS power amplifier with rail-to-rail input and output [J]. Analog Integral Circuits Process, 2006, 46(2) :183
  • 5王为之,靳东明.一种采用共栅频率补偿的轨到轨输入/输出放大器[J].Journal of Semiconductors,2006,27(11):2025-2028. 被引量:6
  • 6杨银堂,李晓娟,朱樟明,韩茹.低压低功耗运算放大器结构设计技术[J].电路与系统学报,2005,10(4):95-101. 被引量:6

二级参考文献32

  • 1段晓峰,陈向东,黎文模.0.5umCMOS工艺参数电流反馈运算放大器[J].微计算机信息,2006(04Z):234-236. 被引量:6
  • 2S Karthikeyan, S Mortezapour, A Tamineedi, et al. Low Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration [J].IEEE Trans. Circuits and Systems Ⅱ: Analog and Digital Signal Processing, 2000, 47(3): 176-184.
  • 3Lin C H, M lsmail. A Low-Voltage Low-Power CMOS OpAmp with Rail-to-Rail Input Output [A]. IEEE Trans. Circuits and Systems,Proceedings of the 40th Midwest Symposium on [C]. 1997. 1193-1196.
  • 4J H Huijsing, D Linebarger. low-Voltage Operational Amplifier with Rail-to-Rail Input and Output Ranges [J]. IEEE J. Solld-State Circuits,1985, SC-20(6): 1144-1150.
  • 5S Akurai, M Ismail. Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage [J]. IEEE J. Solld-State Circuits, 1996, 31(2): 146-156.
  • 6R Hogervorst, J P Tero, J H Huijsing. Compact CMOS constant-gm rail-to-rail input stages with gm controlled by an electronic Zener diode [J].IEEE J.Solld-State Circuits, 1996, 31(7): 1035-1040.
  • 7K Nagaraj. Constant transconductance CMOS amplifier input stage with rail-to-rail input common mode voltage [J]. IEEE Trans. Circuits Systems Ⅱ, 1995, 42(5): 366-s368.
  • 8G Ferri, W Sansen. A rail-to-rail constant-gm low-voltage CMOS operational transconductance amplifier [J]. IEEE J,Solid-State Circuits,1997, 32( 10): 1563-1567.
  • 9Wang M, T L Mayhugh, Jr S H K Embabi, et al. Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition regions [J].IEEE J. Solid-State Circuits, 1999, 32( 10): 148-156.
  • 10Abdulkerim L Coban, Phillip E Allen. A 1.75V Rail-to-Rail CMOS Op-Amp [A]. IEEE Trans.Circuits and Systems, 1994. ISCAS. IEEE International Symposium [C]. 1994, 5: 497-500.

共引文献12

同被引文献13

  • 1翟艳,杨银堂,朱樟明,王帆.一种基于SOC应用的Rail-to-Rail运算放大器IP核[J].西安电子科技大学学报,2005,32(1):112-115. 被引量:3
  • 2Kush Gulati, Hae-seung Lee. A high-swing cmos teles-copic operational amplifier[J]. IEEE J Solid-state Circuits, 1998, 33(12): 2010-2019.
  • 3Wang Jin, Qiu Yulin. Analysis and Design of Fully Differential Gain-Boosted Telescopic Caseode Op-amp[J]. Solid-state and Integrated Circuits Technology, 2004, 2: 1457-1460.
  • 4Feng Wang, Harjani R. Optimal Design of Op amps for Oversampled Converters [C]. IEEE Custom Integrated Circuits Conference,1996: 337-340.
  • 5Weixun Yan, Zimmermann H. Continuous-Time Common-Mode Feedback Circuit for Application with Large Output Swing and High Output Impedance[C].IEEE DDECS, 2008.
  • 6Ojas Choksi, L. Richard Carley. Analysis of Switch-Capacitor Common-Mode Feedback Circuit[J]. IEEE Trans Circ Syst II: Analog and Digital Signal Processing, 2003, 50(12): 906-917.
  • 7V. Iyengar, K. Chakrabarty and E.J. Marinissen. "Test Wrapper and Test Access Mechanism Co-Optimization for System-on- Chip". J. Electronic Testing: Theory and Applications, vol. 18, pp. 213-230, Apr. 2002.
  • 8Y.Huang et al.Resource allocation and test scheduling for concurrent test of core-based SOC design.Proc.Asian Test Symp. 2001.265-270.
  • 9E.J.Marinissen and S.K.Goel.Analysis of test bandwidth utlilization in test bus anti TestRail architectures in SOCs.Digest of paper's of DDECS,2002.52-60.
  • 10V.lyengar,K.Chakrabarty,and E.J.Marinissen.On using rectanglepacking for SOC wrapper,trAM co-optimization.Proc.VLSI Test Symp.,2002.253-258.

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