片上网络关键技术研究

Research of Network on Chip Technology

半导体技术的快速发展以及芯片上系统应用复杂度的不断增长,使得片上互连结构的吞吐量、功耗、延迟以及时钟同步等问题更加复杂,出现了将通信机制与计算资源分离的片上网络。片上网络设计涉及从物理层到应用层诸多方面的问题,本文给出片上网络设计的一些关键技术:设计流程、拓扑结构、路由技术、交换技术、性能评估;并指出目前研究存在的问题和今后的研究方向。

With the development of VLSI technology and increasing complexity of System on Chip application, comunication architecture on chip design encounters some problems,such as,power,latency and clock synchronization.Network on Chip （NoC） was introduced. NoC involves in many problems ranging from physical layer to application layer, the paper provides the key technology for NoC design, such as design flow ,topology, routing, performance evaluation, flow control, resource network interface. In the end,the problems in present research and future research trends are presented.