期刊文献+

一种灵活的包含嵌入式存储器的FPGA结构 被引量:1

Versatile Architecture for FPGAs with Embedded Memory
下载PDF
导出
摘要 近年来,集成电路制造工艺的巨大提高使得FPGA有能力实现大的数字系统电路。这些大的系统通常需要大量的存储器以存储数据。很多FPGA生产商已经推出了含有大的嵌入式存储器的FPGA芯片。然而,大多数学术方面的CAD工具只针对于同质的FPGA结构(即只包括逻辑模块和布线通道的FPGA结构)。FPGA的布线结构通常被表示为RRG(布线资源图)。本文将介绍一种包含嵌入式存储器模块的FPGA的灵活结构以及一种建立RRG的方法。文中我们对VPR(versatile placing and routing)进行了改进,使得VPR可以处理包含嵌入式存储器结构的FPGA的布局布线问题,同时保持了VPR的灵活性。 Recent dramatic improvements in integrated circuit fabrication technology have led to Field-Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems. These large systems often require significant amounts of storage. FPGAs with large embedded memory arrays have been supplied by FPGA vendors. However, most of academic FPGA CAD tools target homogeneous FPGAs (one type of routing channel and function block). FPGA routing architectures are usually represented as a routing resource graph (RRG). In this paper we present a versatile architecture for FPGAs with embedded memory and the scheme to build the RRG. Our enhancements to the VPR (Versatile Place and Route) extend its functionality to FPGAs with embedded memory, while not reducing the versatility at all.
出处 《微计算机信息》 北大核心 2008年第20期219-220,97,共3页 Control & Automation
关键词 场可编程逻辑阵列(FPGA) 嵌入式存储器 RRG VPR FPGAs Embedded Memory RRG VPR
  • 相关文献

参考文献10

  • 1V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers,1999.
  • 2Xilinx, Inc., Application notes: Sparton-3 FPGA Family, March 1,2005.
  • 3J. Rose and S. Brown, "Flexibility of interconnection structures for field-programmable gate arrays," IEEE Journal of Solid-State Circuits, vol. 26, pp. 277-282, March 1991.
  • 4S.J.E. Wilton, J. Rose, Z.G. Vranesic, "The Memory/Logic Interface in FPGA" s with Large Embedded Memory Arrays", IEEE Transactions on Very-Large Scale Integration Systems , vol. 7, no. 1, March 1999
  • 5V. Betz and J. Rose, "Automatic Generation of FPGA Routing Architectures from High-Level Descriptions," ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 175 - 184.
  • 6C. Ebeling, L. McMurchie, S. A. Hauck and S. Bums, "Placement and Routing Tools for the Triptych FPGA," IEEE Trans. on VLSI, Dec. 1995, pp. 473 - 482.
  • 7A. Marquardt. V. Betz and J. Rose, "Timing-Driven Placement for FPGA." ACMISIGDA International Symposium on Field Programmable Gate Arrays. 2000.
  • 8Wong, T.; Wilton, S.J.E., "Placement and routing for nonrectangular embedded programmable logic cores in SoC design". Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on 2004 Page(s):65 - 72
  • 9David Lewis, Vaughn Betz, "The StratixTM Routing and Logic Architecture", FPGA' 03, February 23-25, 2003, Monterey, California, USA.
  • 10苏彦鹏,薛忠杰,须自明,韩磊.一种改进的嵌入式存储器测试算法[J].微计算机信息,2007(01Z):110-112. 被引量:6

二级参考文献5

  • 1曹海源,孙世宇,张志红.一种可编程的通用存储器仿真测试系统[J].微计算机信息,2005,21(4):84-85. 被引量:8
  • 2S.Hamdioui,Z.A1-Ars,and A.J.van de Goor,"Testing static and dynamic faults in random access memories,"in Proc.VLSI Test Symp.,2002,pp.395-400.
  • 3S.Hamdioui,A.J.van de Goor and M.Rodgers,“March SS:A Test for All Atatic Simple RAM Faults,”In Proc.Of the IEEE Int.Workshop on Memory Technology,Design and Testing,Bendor,France,pp.95-100.
  • 4S.Hamdioui,Z.Al-Ars,and A.J.van de Goor,“Linked faults in random access memories:concept,fault models,test algorithms,and industrial results,”In IEEE Trans.On Computer-Aided Design of Integrated Circuits and Systems,Vol.23,No.5,pp.195-205,May 2004.
  • 5R.Dekker,F.Beenaker,and L.Thijssen,"A realistic Fault model and test algorithm for static random access memories,"IEEE Trans.Computer-Aided Design,Vol.9,pp.567-572,June 1990.

共引文献5

同被引文献2

  • 1IDT公司.IDT71V547S使用说明书[EB/OL].[2006-10-01].http://www.idt.com.
  • 2SHARP公司,LQ064V3DG01 TFT-LCD模块使用说明书[EB/OL].[2006-11-02].http://document.sharpsma.com/files/LQ064V3DG01_SS_110206.pdf.

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部