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基于自身可信度的低复杂度LDPC码位翻转解码算法 被引量：2

Self Reliability Based Low Complexity Bit-flipping Decoding Algorithm for LDPC Codes
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摘要 提出一种基于位翻转的低复杂度、便于硬件实现的LDPC码解码算法.该算法充分利用变量节点的本征信息来计算翻转判决函数,减少了对其它变量节点软信息的需求,因此大大降低了解码硬件实现的复杂度,同时保证翻转判决函数具有较高的可靠性.利用该算法,对RS-based LDPC码进行的仿真结果表明,改进算法的解码性能接近甚至略优于IMWBF算法. A new low complexity and implement efficient bit-flipping decoding algorithm for Low-Density Parity-Check （LDPC） codes is presented in this paper. The proposed algorithm computes the flipping function by the intrinsic value of the message node, and it reduces the requirement of the information from other message nodes. So, it has a lower com- plexity and still guarantees the reliability of the flipping function. The simulation results for RS-based LDPC codes using the proposed algorithm show that it has the performance approaching the IMWBF algorithm or even better.
作者 张仲金 高明伦 沙金 李丽 董岚
机构地区 南京大学微电子设计研究所
出处 《微电子学与计算机》 CSCD 北大核心 2008年第7期92-94,99,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(90307011) 江苏省高技术研究项目(BG2005030)
关键词 LDPC码 位翻转 低复杂度 LDPC codes bit-flipping low complexity
分类号 TP31 [自动化与计算机技术—计算机软件与理论]
  • 相关文献

参考文献6

  • 1Gallager R G. Low density parity check codes [ J ]. IRE Trans. Inform. Theory, 1962(IT- 8) :21 - 28.
  • 2MacKay D J C, Neal R M. Near- Shannon - limit performance of low-density parity- check codes[ J ]. Electron. Lett., 1996(32) : 1645 - 1646.
  • 3徐华.LDPC码相关技术研究[J].微电子学与计算机,2005,22(3):178-180. 被引量：8
  • 4Ming Jiang, Chunming Zhao. An improvement on the modified weighted bit flipping decoding algorithm for LDPC codes[J]. IEEE Commun. Lett., 2005, 9(9) :814- 816.
  • 5Ivana Djurdjevic, Jun Xu. A class of low- density paritycheck codes constructed based on reed- solomon codes with two information symbols[J ]. IEEE Communications Letters, 2003,7(7) :317 - 319.
  • 6Darabiha A, Carusone A C, Kschischang F R. Multigbit/sec low density parity check decoders with reduced in- terconnect complexity[J]. IEEE International Symtx)sium, 2005(5) :5194- 5197.

二级参考文献11

  • 1R G Gallager. Low Density Parity Check Codes[J]. IRE Trans. Inform. Theory, IT-8, Jan. 1962: 21～28.
  • 2C Berrou, A Glavieux, P Thitimajshima. Near Shannon Limit Error-Correcting Coding and Decoding : Turbo Codes [C]. Proc. IEEE ICC'93, Geneva, Switzerland , May 1993.
  • 3D J C MacKay and R N Neal. Near Shannon limit performance of low density parity check codes [J]. IEEE Electronic Letters, Aug. 1996,32: 1645～1646.
  • 4S Y Chung, et al. On the Design of Low Density Parity Check Codes within 0.0045 dB of the Shannon Limit [J].IEEE Commun. Letters, Feb. 2001,5: 58～60.
  • 5R Michael Tanner. A Recursive Approach to Low Coplexity Codes. IEEE Trans. On InformationTheory,September,1981,IT-27(5): 533～547.
  • 6M Sipser, D A Spielman. Expander Codes[J]. IEEE Transactions on Information Theory, November 1996, 42 (6):1710～1722.
  • 7T J Richardson and R L Urbanke. Efficient Encoding of Low-Density Parity-Check Codes[J]. IEEE Trans. Inform.Theory, Feb. 2001,47(2): 638～656.
  • 8T Richardson and R Urbanke. The Capacity of Low-density Parity Check Codes under Message-passing Decoding[J]. IEEE Trans. Inform. Theory, Feb. 2001, vol.47: 599～618.
  • 9D Burshtein and G Miller. Expander Graph Arguments for Message-Passing Algotithms[J]. IEEE Trans. Inform. Theory, Feb. 2001,47(2): 782～790.
  • 10S Y Chung, T J Richardson, and R Urbanke. Analysis of Sum-Product Decoding of Low-Density Parity-Check Codes using a Gaussian Approximation[J]. IEEE Transactions on Information Theory, Feb. 2001,47(2): 657～670.

共引文献7

同被引文献11

  • 1Lin Shu. Error control coding[M].2nd ed. Boston: Prentice Hall, 2002.
  • 2Richardson T J, Urbanke R L. Efficient encoding of low- density parity-check codes[J]. IEEE Transactions on Information Theory, 2001,47(2) :638 - 656.
  • 3Reed L S, Solomon G. Polynomial codes of certain finite fields[J]. Society of Industrial and Applied mathematies, 1960(8) :300 - 304.
  • 4张晨.高吞吐量LDPC码编码构造及其FPGA实现[D].上海:上海交通大学,2009.
  • 5Zongwang Li, Lei Chen, Shu Lin. Efficient encoding of quasi- cyclic low- density parity- check codes[J]. IEEE Transactions on Communications, 2006,54 ( 1 ) : 71 - 81.
  • 6Davide Pellerin, Scott Thibault. Pratical FPGA programming in C[M]. Boston: Prentice Hall PTR, 2007: 19--51.
  • 7Antola A Santambrogio, Fracassi M D, Gotti M, et al. A novel hardware/software eodesign methodology based on dynamic reconfiguration with impulse C and codeveloper[C]// 3rd Southern Conference on Programmable Logic. Mar del Plata, Argentina,2007:221-224.
  • 8Zhang T, Parhi K K. A 54MBPS (3, 6)-regular FP GA LDPC decoder[C]// IEEE SIPS. Canada: British Columbia, 2002 : 127- 132.
  • 9Levine B, Taylor R, Schmit H. Implementation of near Shannon limit error--correct codes using reconfigurable hardware[C]// IEEE Syrup. On FCCM. Los Alamitos,2000:217- 226.
  • 10Andrew J Blanksby, Chris J Howland. A 690--mW 1- Gb/s 1024 b, rate-1/2 low- density parity-check code decoder[J]. Journal of Solid-State Circuits, 2002, 37(3) :404-412.

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微电子学与计算机
2008年 第7期

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