一种输出范围10-600MHz的高性能锁相环

A 10～600MHz High Performance Phase-Locked Loop

在传统锁相环结构基础上设计了一种基于0.18μm CMOS工艺的高速、低功耗、低噪声的高性能混合信号锁相环.测试结果显示,该芯片在1.8V电源供电下,可以提供从10-600MHz的稳定输出信号.同时该芯片输出抖动小,在输出频率152MHz处的峰峰值抖动小于50ps,均方抖动约7ps.锁相环的版图尺寸为560μm×400μm,核心功耗约6mW.

Based on the classic Phase-Locked Loop circuit, a high performance Mixed-Signal Phase-Locked Loop circuit, implemented in 0.18μm CMOS process, is presented. Testing results show that the circuit achieves a wide locking range of 10-600MHz at a 1.8Vpower supply. Also it has a very low peak-to-peak jitter less than 50ps at 150MHz output frequency. The area of the active layout of the PLL is 560μm × 400μm, power consumption is about 6mW.