摘要
研究了单精度浮点数加/减法的结构及其设计方法,并在A ldec公司的Active-HDL软件环境下,采用VHDL语言进行设计,并进行了仿真验证,计算精度可以达到10-7。
The structure and design of adder or subtraction of float-point number with single precision are studied under the Active-HDL software environment of the Aldec company. It is designed and simulated with VHDL, and the precision can reach 10 ^-7 .
出处
《电子工程师》
2008年第7期52-55,共4页
Electronic Engineer
关键词
单精度浮点数
加/减法
VHDL
FPGA
float-point number with single precision
adder or subtraction
VHDL
FPGA
