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低功耗总线编码技术 被引量：2

Low Power Bus Coding Approach
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摘要 为了降低总线翻转率通常对总线进行编码。B-I编码是这些编码方法中比较简单实用的一种编码方法。但在连续传输时,它对翻转率降低不明显。该文对B-I编码加以改进,在编码前进行连续与非连续的判断。在连续传输时采用渐进零翻转编码,从而使得总线进行连续传输时翻转率接近为零。改进后的编码对同一段程序,相对于B-I编码翻转率进一步下降了28.7%,面积增加了18 225μm2。 The method of bus endoding is for cutting down the transition frequency. The Bus-Invert（B-I） coding is the most simple and practical. But the transition frequency reduction is not obviously during the sequential transfer. In this paper, it judges the type of sequential and non-sequential transfer and takes the method of asymptotic zero-transition activity encoding during the sequential transfer. Compared with the B-I coding method for the same program, it can cut down the transition frequency by 28.7% and area increasing byl 8 225μm^2.
作者 尹立群 冯庆 袁国顺
机构地区 中科院微电子研究所 中科院电子学研究所
出处 《计算机工程》 CAS CSCD 北大核心 2008年第15期238-240,共3页 Computer Engineering
关键词 先进微控制器总线结构 低功耗设计 总线编码 翻转率 B-I编码 Advanced Micro-controller Bus Architecture（AMBA） low-power design bus coding transition frequency Bus-Invert（B-I） coding
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献7

  • 1Weste N, Eshraghiam K. Principles of CMOS VLSI Design[M]. MA, USA: Addison-Wesley Publishing Company, 1998.
  • 2Chandrakasan A E Sheng S, Brodersen R W. Low-power CMOS Digital Design[J]. IEEE J. Solid-State Circuit 1992, 27(4): 473-484.
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同被引文献33

  • 1Wang W, Mishra P. PreDVS: Preemptive dynamic voltage scaling for real-time systems using approximation scheme[C] //Proc of the 47th Design Automation Conf. Piscataway, NJ: IEEE, 2010:705-710.
  • 2Cao Z, Foo B, He L, et al. Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications [J]. IEEE Trans on Circuits and Systems,2010, 67(3): 681-690.
  • 3Teng S K, Soin N. Low power clock gates optimization for clock tree distribution[C] //Proc of the llth Int Symp on Quality Electronic Design 2010. Piscataway, NJ: IEEE, 2010: 488-492.
  • 4Ahuja S, Wei Z, Lakshminarayana A, et al. A methodology for power aware high-level synthesis of coprocessors from software algorithms [C]//Proc of the 23rd Int Conf on VLSI Design. Piscataway, NJ: IEEE, 2010: 282-287.
  • 5Devlin B S, Nakura T, Ikeda M, et al. A low power and high throughput self synchronous FPGA using 65 nm CMOS with throughput optimization by pipeline alignment [J]. IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, 2010, 93(7) : 1319-1328.
  • 6Mohammad B. Low leakage power SRAM cell for embedded memory[C] //Proc of 2011 Int Conf on Innovations in Information Technology (IIT). Piscataway, N J: IEEE, 2011: 367-370.
  • 7Jiongyao Y, Watanabe T. A variahle hitline data cache for low power design [C]//Proc of 2010 Asia Pacific Conf on Postgraduale Research in Microelectronics and Electronics. Piscataway, NJ: IEEE, 2010:174-177.
  • 8Jiongyao Y E, Watanabe T. An adaptive width data cache for low power design [C] //Proe of 2009 Int SoC Design Conf. Piscataway. N J: IEEE, 2009:488-491.
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  • 10Lee C. Lee J K, Hwang T, et al. Compiler optimization on VLIW instruction scheduling for low power[J]. ACM Trans on Design Automation of Electronic Systems, 2003, 8 (2) : 252-268.

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计算机工程
2008年 第15期

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