基于VHDL的数字时钟的设计

Design of digital clock based on VHDL

随着EDA技术的发展和应用领域的扩大与深入,EDA技术在电子信息、通信、自动控制及计算机应用领域的重要性日益突出。EDA技术就是依赖功能强大的计算机,在EDA工具软件平台上,对以硬件描述语言VHDL为系统逻辑描述手段完成的设计文件,自动地完成逻辑优化和仿真测试,直至实现既定的电子线路系统功能。本文介绍了基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧。在QuartusⅡ开发环境中编译和仿真了所设计的程序,并逐一调试验证程序的运行状况。仿真和验证的结果表明,该设计方法切实可行,该数字时钟具有一定的实际应用性。

With the development of EDA technology and expansion and deepen of application, EDA technology has become more and more important in electronic information, communications, automatic control and computer applications. EDA technology depends on powerful computers, complete logic optimization and simulation tests of design documents by means of making hardware description language VHDL as the system logic description automatically in EDA tools software platform, until it has achieved the function of established electronic circuits system. In this paper, we have introduced ideas and craftsmanship of multi-function digital clock design based on VHDL hardware description language. Compile and simulate designed procedures in Quartus Ⅱ development environment and debug and verify each of the operation of program. Simulation and verify results show that this design is workable and this digital clock is practical.