摘要
实现一个8通道10 b转换精度的逐次逼近式(SAR)模拟-数字转换器。在DAC的设计上采用新的电阻电容混合式的DAC的结构,和传统的C-R式结构相比具有更小的面积。同时对比较器的设计进行了优化,采用一个三级级联的准差分结构,并设计在传统的前置预放和锁存器级联的理论基础上,引入了交叉耦合负载,复位、钳位技术,获得了高精度和较低的功耗。设计经HSPICE仿真结果证明有效,并采用0.13μm CMOS工艺,分别采用2.5 V的模拟电源电压和1.2 V的数字电源电压供电,实现10位的精度。芯片面积为480μm*380μm,FF case下功耗为0.54 mW。实现了超低功耗的ADC的设计。
An IP core of an 8 - channel 10 - bit SAR ADC is designed in this paper. An optimal Resister - Capacitor hybrid D/A structure based on their good qualities and disadvantage,this kind of D/A structure has smaller size than Capacitor-Resister hybrid structure. A comparator with resetting and clapping method on the basis of conventional preamplifier and flip - latch, which is consisted of an quasi-differential structure is developed. These proposed methods are validated by the result of simulation with HSPICE. The design adopts 0.13μm CMOS technology,operates with 2.5V analog power and 1.2V digital power supply. The simulation results show that this design can achieve 10 - bit resolution. The area of IP core is 480μm ＊ 380μm,at FF case,Power Dissipation is 540μW. As a result,ADC design with low - power consumption and small area is implemented.
出处
《现代电子技术》
2008年第9期83-86,共4页
Modern Electronics Technique
关键词
模数转挟器
逐次逼近
准差分
比较器
IP核
analog - to - digital converter, successive approximation, ISO - differential
comparator
IP core
