一种专用集成电路功能测试仪的设计与实现

On Development of a LowCost Chinese Chip Tester

采用现场可编程门阵列（ＦＰＧＡ）技术设计与实现了一种低成本、高性能的专用集成电路（ＡＳＩＣ）功能测试仪——ＮＰＵＡＳＩＣ测试仪。测试管脚多达１２８路，每路独立可编程，具有多种测试模式，可测试静态和动态芯片，并具备初步的速度测试能力。该测试仪是在ＩＢＭＰＣ及其兼容机上开发的，操作系统为ＤＯＳ；测试环境成熟，提供了与Ｃ兼容的高级测试语言，并可与当前几种广泛使用的电子设计自动化（ＥＤＡ）工具接口。

Imported chip testers are not in wide use in China due to their highcost. We at NPU (Northwestern Polytechincal University) have successfully developed a lowcost but still fairly high quality functional chip tester called by us NPU ASIC (applicationspecific integrated circuit) chip tester. Fig.1 shows the architecture of NPU ASIC chip tester. With this architecture, the tester can provide three test modes (related to controller denoted as A in Fig.1 and test vector memory denoted as B in Fig.1) and can do primary speed testing (related to programmable delay unit denoted as C in Fig.1). C in Fig.1 is capable of programming for as short as 5ns. Double buffer technology developed by us is related to drive unit denoted as D in Fig.1. Double buffer technology makes it possible to transmit simultaneously all stimulus signals received from B by D to device under test denoted as E in Fig.1. Double buffer designed by us is shown schematically in Fig.3. We implemented NPU ASIC chip tester with high density FPGA(field programmable gate array) chips in order to make it smaller, integrated, highly reliable, and inexpensive. By means of the test aid software package developed by ourselves, NPU ASIC chip tester is friendly to the user. It can provide C compatible test language, waveform display, and the interfaces to popular EDA(electronic design automation) tools.