基于FPGA的BiSS协议光电编码器通信模块设计

Design of communication module of BiSS protocol electric encoder based on FPGA

本文完成了基于BiSS协议的绝对位置式光电编码器的通信模块设计。该通信模块以10Mb/s波特率读取光电编码器数据,单次读取耗时仅需4.2μs,是其它同类常用通信协议速度的5倍以上。文中给出了BiSS协议与同类常用协议关键特性的对比,表明其具有通信速度较快、误码率较低、工业应用适应性较强、成本较低等优点。该通信模块基于CycloneI系列的FPGA设计,使用Verilog HDL编写,实验结果表明,模块通信速度较快,工作稳定。

A communication module of BiSS protocol absolute rotary electric encoder is accomplished. It costs only 4. 2μs to read one position data of the encoder at 10 Mb/s, at least 5 times faster than other protocol time. Comparison between BiSS and other popular protocol shows that BiSS system is much faster, as well as with fewer communication mistakes, stronger application adjustment, lower system cost. The module is designed based on Cyclone I FPGAs, programmed with Verilog HDL, and it works stably at high speed in experiments.