虚拟数字存储示波器中A/D动态性能的研究

Study on A/D dynamic performance of virtual digital storage oscilloscope

研究并设计了一种高速高精度的虚拟数字存储示波器。采用理论分析和数值仿真的方法研究了调理电路噪声和采样时钟相位噪声对A/D动态性能的影响,以此为指导设计出了独立双通道100MSPS采样率、10位垂直分辨率的虚拟数字存储示波器。研究表明,调理电路的噪声和采样时钟的相位噪声会对系统的动态性能产生严重影响,实验还发现,调理电路的谐波失真也是降低系统动态性能的重要因素,因而在高速高精度数据采集系统中应该选择低噪声和低谐波失真的器件,同时需要优化PCB设计。

A high speed and high resolution virtual digital storage oscilloscope was studied and designed. By means of theoretical analysis and digital simulation, the effect of conditioning circuit noise and sampling clock phase jitter upon A/D dynamic performance was investigated. Accordingly a high dynamic performance virtual digital storage oscilloscope with dual channels was developed, which reaches the sampling speed of 100 MSPS and the vertical resolution of 10 b. The study indicates that conditioning circuit noise and sampling clock phase jitter remarkably affect the dynamic performance, and experiment also shows that conditioning circuit harmonic distortion is an important factor to degrade the system dynamic performance. So the designer should choose the parts with low noise and low harmonic distortion, and additionally optimize the PCB design.