一种变步长锁频基带信号时钟提取方法

A variable step length frequency locked method of baseband signal clock extraction

串行数字通信系统需要从一个串行数据流中抽取一个采样时钟.这个抽取通常由一个叫时钟及数据恢复单元的非线性电路实现,该电路负责跟踪信号中的低频相位变化.本文提出了一种从频率上跟踪、锁定基带信号发端时钟频率从而提取出基带信号时钟的方案.此方法比传统的锁相环提取时钟具有更好的性能.由于它适于采用硬件语言描述,因而可集成在各类数字芯片中.

Serial digital communication systems require the extraction of a sampling clock from a serial stream. Usually, this extraction is performed by a non-linear circuit called a Clock and Data Recovery （CDR） unit. The CDR is responsible for tracking low frequency phase changes in the signal. In this paper, a new scheme of extraction baseband signal clock is put forward. With this method, a better clock can be extracted from baseband signal because clock frequency of transmitter is locked by clock frequency of receiver. In addition, it applies to description with HDL, so it can be integrated in all kinds of digital chips easily.