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高性能连续时间Sigma-Delta调制器系统级设计 被引量：4

Architecture Design of a High Resolution Continuous-Time Sigma-Delta Modulator
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摘要 介绍了高性能连续时间Sigma-Delta调制器的系统设计和行为级建模的方法,并通过在噪声整形滤波器中加入一对零点改善了调制器带内信噪比.仿真结果显示,该调制器适用于转换精度14位,转换速率7.8Msps的多bit连续时间Sigma-Delta A/D转换器. Illuminated by a real design case, an architecture design method of high resolution multi-bit continuous-time Sigma-Delta modulator is presented. A test-bench for the further circuit design is also introduced. Simulation results show that the modulator achieves a 14bits and 7.8Msps resolution.
作者 褚子乔 王东辉 侯朝焕
机构地区 中国科学院声学研究所
出处 《微电子学与计算机》 CSCD 北大核心 2008年第8期45-47,51,共4页 Microelectronics & Computer
关键词 SIGMA-DELTA调制器 过采样 连续时间 多bit量化 Sigma-Delta modulator over-sampling continuous-time multi-bit
分类号 TN4 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献6

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二级参考文献15

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共引文献6

同被引文献26

  • 1李罗生,洪缨,侯朝焕.一种高性能的Σ-ΔA/D转换器的设计[J].微电子学与计算机,2005,22(1):136-139. 被引量：7
  • 2沈佳铭,洪亮,石春琦,张润曦,李小进,赖宗声.一种可重构的24bitΣ-Δ调制器的设计[J].微电子学与计算机,2007,24(4):159-162. 被引量：5
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引证文献4

二级引证文献3

微电子学与计算机
2008年 第8期

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