基于DA算法的1-D DCT IP核结构设计

Design of 1-D DCT IP Core Structure Based on Distributed Arithmetic

提出了一种基于DA(Distributed Arithmetic)算法的1-D DCT IP核结构.该结构采用无乘法器的结构设计:为提高速度,设计了两位串行分布算法结构,并对数据采用流水线方式进行处理;为减小面积,采用了OBC编码方式进行查表,将ROM的大小表由2N减小到2N-1.最后给出了FPGA实现和仿真结果,验证了该设计的正确性,满足了数据处理的实时性要求.

This paper presents a design of 1-D DCT IP core structure based on Distributed Arithmetic （DA）. This structure has none multiplier, 2 bits serial DA structure is designed and pipelining style is applied to the data flow, which can make the design achieve high speed operation; To reduce hardware requirement, OBC technology is taken, which cuts down the size of a ROM table from 2^N to 2^N-1. At the end of this paper, the FPGA implementation and simulation results are provided, which confirm the truth of the design and achieve high speed operation.