数字电视解调芯片的可测试性设计与优化

DFT Implementation and Optimization of the Demodulator Chip in DVB-T System

介绍了VLSI芯片的测试技术及故障模型,针对一款数字电视接收系统解调芯片,从设计中不同的阶段分析了集成电路的可测试性设计及其优化,解决了由于集成大量存储器引起的测试覆盖率低的问题,完成了该芯片满足时序要求的可测试性设计及优化过程,达到了流片要求.

This paper focuses on this problem and takes a digital TV demodulation chip as example, analyzes the DFT（Design-For-Test） design and its optimization techniques in different design stage, achieves the expected coverage, and the requirements of tapeout are also satisfied. Namely, the method and optimization works applied here greatly improve DFT quality and its test coverage.