GPS接收机相关器技术研究及FPGA实现

GPS Correlator Research and FPGA Implementation

GPS接收机中的相关器设计是GPS接收机设计的一个关键技术之一。阐述了GPS相关器的工作原理和结构,对构成相关器的各个模块进行了详细的理论分析,利用本地产生的C/A码的超前、即时、滞后码与输入信号进行并行相关,提高了捕获的速度和精度,并用verilog硬件描述语言在FPGA中实现了GPS相关器的全部设计。设计中首先在modelsim下进行功能仿真,然后进行时序仿真,仿真通过后下载到Xilinx VirtexTM-II Pro开发板中进行验证。运行结果表明设计的相关器工作正常,性能可靠,与微处理器配合可以完成GPS信号的捕获和跟踪。

The design of GPS correlator is one key technique in GPS receiver. The operation principle and the structure of GPS Correlator were explained, and all the modules of the correlator were studied. The local C/A code loop generated three outputs： an early code, a late code, and a prompt code. Using the three outputs, the parallel correlation was developed and it improved the acquiring performance of efficiency and accuracy of the GPS receiver. All the schemes of GPS correlator were implemented by Verilog hardware description language and simulated under the environment of Modelsim software, then validated on the Xilinx Virtex^TM-H Pro development board. The results demonstrate that the correlator can incorporate with microprocessor to realize the acquisition and tracking function of the GPS signal normally and reliably.