基于16 bit Sigma-Delta模数转换器的数字滤波器设计

Digital Filter Design for 16 bit Sigma-Delta A/D Convertor

介绍了基于64倍过采样sigma-delta模数转换器的多级抽取滤波器设计。通过采用低功耗的多相分解梳状滤波器结构来代替传统的CIC滤波器结构,使得梳状滤波器部分的功耗降低近5倍。通过对滤波器电路结构的优化,可节省35%的芯片面积占用量。经过仿真及FPGA验证,该滤波器的信噪比达到99dB,可以实现16位精度模数转换器的设计要求。

This paper introduces a class of multi-stage FIR decimators for sigma-delta analog-to-digital convertor. By using the low power polyphase comb filters structure, the proposed comb filter has 5 times less power consuming compared to conventional CIC filter. And by optimizing the structure of the circuit,it can save 35% chip area, leading to low cost and low power consumption. The SNR of the filter is 99 dB,and it can realize 16 bits resolution A/D convertor.