一种16.9mW 10 bit 50 Msample/s流水线ADC IP核设计

A 16.9 mW 10 bit 50 Msample/s Pipelined ADC IP Core

设计了一个10位50Msample/s流水线ADCIP核。采用SMIC0.25μm1P5M数字CMOS工艺,通过使用运算放大器共享技术、电容逐级缩减技术和对单元电路的优化,使得整个IP核面积仅为0.24mm2。仿真结果表明,在50MHz采样率、输入信号为2.04MHz正弦信号情况下,该ADC模块具有8.9bit的有效分辨率,最大微分非线性为0.65LSB,最大积分非线性为1.25LSB,而整个模块的功耗仅为16.9mW。

A 10 bit 50 Msample/s pipelined analog-to-digital converter（ADC） IP core is presented. The ADC core is designed in SMIC 0. 25 μm 1P5M CMOS process. The layout size of 0. 24 mm^2 is achieved by using OPAMP sharing technique and capacitors scaling technique. Simulation results show that it achieves an ENOB of 8. 9 bit, a maximum DNL of 0. 65 LSB, a maximum INL of 1.25 LSB for a 2. 04 MHz input at full sampling rate. The total power consumption of the ADC core is only 16.9 mW.