基于可重构SOC平台的嵌入式MPEG2解码器设计

Embedded MPEG2 Decoder Design Based on A Reconfigurable SOC Platform

利用FPGA的可重构特点,建立一个可重构的SOC设计平台。该平台第一层为可重构的FPGA,第二层为利用FP-GA资源搭建的LEON2SOC系统,由RISC处理器软核、AMBA总线以及IP模块结构组成,第三层是应用层,在SOC系统的基础上实现各种应用。为了实现这个目标,SOC系统中的IP模块应该具有两个特点:即插即用和参数化。基于该平台,成功实现了嵌入式MPEG2视频解码器的不同应用。证明了可重构的设计平台能够满足不同的应用需求。

Utilizing the reconfigurable characteristics of FPGA, a reconfigurable LEON2 SOC platform including RISC processor soft core, AMBA bus and pre-defined IP platform block structures （e. g. , co-processor, bus master, bus slave） is designed for versatile application developments. To achieve this goal, each IP of target application should be mapped into the pre-defined IP platform block structures with two features, plug-and-play and parametrizable. Having these features, this platform provides a versatile infrastructure for application development with fast turn-around. On this platform, an embedded MPEG2 decoder is successfully designed.