一种用于SDH2Mb/s支路输出口的全数字锁相环

An All Digital PLL for E1 Clock Recovery in SDH Systems

提出了一种具有极低通带宽度的二阶全数字销相环，并采用了一些非线性的改进措施，从而使其具有一个相对较宽的牵出范围，以恢复E1支路信号的时钟。硬件实验证实，它完全可以满足ITU－T对抖动抑制特性的要求。同时由于数字集成电路技术成熟，其集成度远远高于模拟集成电路；因而采用全数字锁相环对系统的集成有明显的益处。

In this paper, a second-order all digita Phase-Locked Loop (PLL) with a very narrow bandwidth is proposed, and some nonlinear methods are used so that this PLL has a much wider pullout range. This PLL could be used to recover the E1 clock that is demapped from TU-12 signal.It is proved by hardwareexperiment that the performance can meet the IUT-T recommendation.All digital circuits are useful in VLSI design.