适合硬件实现的JPEG2000码率控制算法及其VLSI结构设计

Hardware-oriented rate control algorithm for JPEG2000 and its VLSI architecture design

为了简化硬件实现的复杂度和降低存储量,提出一种采用码率预分配的JPEG2000码率控制算法,并给出相应的VLSI结构设计.原始图像经过小波变换和量化后,对EBCOT码块的有效比特平面进行独立熵估计,计算出所有码块的估计熵总和.依据每个码块的估计熵在所有码块的估计熵总和中所占的比例,指导分配每个码块的码率,EBCOT编码器根据分配到的码率实时截断码流和编码通道,减少了T1编码的时间.码块经过T1编码后直接打包输出,无需率失真斜率计算和率失真优化截取.实验结果表明,本算法很大程度上减少了编码计算量和存储量,易于硬件实现.

For the purpose of decreasing the quantity of operation and reducing the size of memory, a new rate control algorithm for JPEG2000 is proposed utilizing the rate pre-allocation method, the VLSI architecture design of which is given as well. After wavelet transform and quantification on the original image, a prediction module is introduced to estimate the entropy of the EBCOT code block within the available bit-plane, and then the proportion between the estimate entropy of each code block and the summation estimate entropy of all code blocks is used to allocate the rate for each code block. EBCOT coder truncates the code stream according to the allocated rate, and thus the operation time consumed by the T1 coder is reduced. After coded by the T1 coder, each code block can be packed to the output, with no need for computing the rate-distortion slope and completing the rate-distortion optimization truncation. Experimental results show that the proposed algorithm can efficiently reduce the cost of computation and memory usage, and that it is most suitable for hardware implementation.