无线传感网低功耗Rake接收机VLSI设计与实现

VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks

针对近地无线信道变化多端的多径现象,该文提出了一种用于复杂信道环境下的低功耗无线传感网Rake接收机VLSI方案并在FPGA上实现。仿真和应用表明,该Rake接收机不仅具有良好的抗多径衰落性能,而且与常规Rake接收机相比,显著节省了VLSI资源并降低了功耗。

A low-power VLSI Rake receiver is proposed and realized on FPGA for wireless sensor networks used in complicated wireless environments. Low-power design strategies including reducing clock frequency, sharing of models and dynamic sleeping control are used to reduce the power consumption in order to fit the energy limitations in wireless sensor networks. Simulations and applications show that the receiver can specially reduce VLSI resource and power consumption compared to ordinary Rake receiver.