基于FPGA的数字锁相环的研究与实现

Design on Digital Phase Locked Loop Based on FPGA

介绍了当前广泛应用的数字锁相环的原理和基于FPGA的设计方法。针对在数字锁相环应用中,当滤波器K值较小时存在的相位抖动问题,提出了一种锁定检测模块的设计,通过仿真验证,该设计能够有效地抑制锁定状态下的相位抖动。

An all digital phase locked loop based on FPGA is presented. Compared with the method once widely used, a new module - phase - locked detector is proposed, which can deal with the problem of phase jitter. Key technology and implementation of the circuit is discussed and simulated.