基于FPGA的图像中值滤波算法硬件实现

The Realization of Image Median Filter Algorithm Based on FPGA

提出一种适于硬件并行处理的图像快速中值滤波算法,并用VHDL硬件开发语言在Altera公司的现场可编程门阵列(FPGA)上实现,给出了整个硬件系统的构造方法,以128×128×8bit的灰度图像滤波处理实验结果表明,该方法可实时进行中值滤波,适于图像采集与预处理系统。

In this paper, a fast median filtering algorithm is proposed for parallel image processing on hardware. The algorithm is executed in the FPGA of Ahera using VHDL. The building method of the entire hardware system is provided. The experimental results on filtering of 128×128×8bit grey-level images show that the proposed method is applicable for real-time median filtering and the image acquisition and pre-processing system.