基于噪声分析的低抖动全数字锁相环的设计

Design of a Low-Jitter All-Digital Phase-Locked Loop Based on Noise Analysis

设计了一个用于时钟产生的全数字锁相环（ADPLL），其数控振荡器（DCO）采用9级环形振荡器，每级延迟单元的延迟时间均是可调的，各级倒相器的尺寸经过精确设计。该电路基于SMIC0．13μm CMOS工艺，采用1．2V电源供电，整个芯片的面积为0．13485mm^2。示波器测试结果表明，锁相环的捕获频率范围为100-500MHz，输出频率为202．75MHz时，峰一峰值抖动为133ps，RMS抖动为46ps。

A low-jitter all-digital phase-locked loop （ADPLL） was designed, which was used as a clock generator. The digitally-controlled oscillator （DCO） for this ADPLL was a nine-stage ring oscillator with changeable delay in each stage and the size of inVerters in each stage was carefully designed. Implemented in a 0. 13 μm CMOS process with 1. 2 V supply voltage, the circuit occupied a chip area of 0. 1348 mm^2. Results measured on oscillograph showed that the ADPLL had a capture frequency range from 100 MHz to 500 MHz, a peak-to-peak jitter of 133 ps and an RMS jitter of 46 ps for DCO output frequency of 202.75 MHz.