扫描电路测试功耗综述

Summary of Test Power of Scan Circuit

随着集成电路制造技术的发展,高集成度使得测试时的功耗成为集成电路设计必须考虑的一个重要因素,低功耗测试也就成为了测试领域一个令人关注的热点。目前,低功耗测试技术的研究还在发展之中,工业生产中低功耗测试方法还没有得到充分的应用。在集成电路中采用扫描结构的可测试性设计方法,能够提高测试覆盖率,缩短测试时间,已在集成电路测试中得到大量应用。基于扫描结构的数字集成电路,学术界已提出了许多方法降低该电路的测试功耗,本文对此方面的研究进行综述。随着测试技术的发展,测试功耗的理论也将日益深入。

With the development of VLSI manufacture technology and the higher integration degree, test power consumption has become one of the main concerns of IC designers. Right now the research of low power consumption test method is in developing, and it doesn＇t take full advantage in the industry. Scan circuit, for the high test coverage and low time cost, is widely used in the IC DFT test. There are many kinds of low power test theory in academe based on the scan circuit, which will be summarized in this paper.