摘要
为了降低NOR结构快闪存储器的编程时间,本文提出一种能够根据编程数据的特点改变编程脉冲时序的快速页编程算法。它通过一个简单的判断电路对输入的编程数据中"1"的个数进行判断,并在状态机的控制下产生具有最小编程时间的页编程脉冲时序,从而达到缩短页编程时间的目的。统计结果表明,本算法的页编程时间不到传统方法的70%。
In order to reduce the program time of NOR flash memory, a novel fast page programming algorithm, which generates different timing sequence for the program data with different l＇s, is proposed in this paper. It involves a detector circuit to examine the l＇s in the program data, and then the state machine takes these outputs of the detector circuit to generate the proper timing sequence with shortest program time. The statistics result shows that the whole page program time is less than 70% compared to that of the traditional method.
出处
《电路与系统学报》
CSCD
北大核心
2008年第4期116-119,共4页
Journal of Circuits and Systems
基金
国家"八六三"高技术项目(2003AA1Z1420)
关键词
快闪存储器
NOR结构
编程算法
状态机
flash memory
NOR architecture
programming algorithm
state machine
