摘要
常用的线性卷积方法要求两个输入序列的持续时间相同,但在实际工程中经常会遇到某个输入序列具有较长持续时间的情况,从而无法达到信号"实时"处理的要求。在这种情况下,分段卷积是一种有效的解决方案。设计了一种分段卷积快速算法模块,在FPGA中采用流水线结构进行实时处理。经检验该方法正确且能很好地满足对信号进行实时处理的要求。
The linear convolution usually needs two finite -time input sequences, but in the actual application, one of the input sequences is very long, so linear convolution canr t process the data in a real- time. On this situation, the partition convolution is an effective solution. This paper proposes a fast algorithm of partition convolution module, using pipeline structure in FPGA to real - time operate the data. The practical results indicate that this method is correct and elective.
出处
《现代电子技术》
2008年第17期146-147,150,共3页
Modern Electronics Technique
关键词
分段卷积
实时处理
重叠相加法
FPGA
partition convolution
real - time processing
overlap - add method
FPGA
