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Review and Perspective of Architecture Development for Dynamic Random Access Memory

Review and Perspective of Architecture Development for Dynamic Random Access Memory
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摘要 Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory(DRAM) applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor(Fin-FET), Wafer bonded double gate and silicon on nothing(SON) gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/silicon(PIS) capacitors to the metal/insulator/metal(MIM) capacitors used for today 50nm technology node and below. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in DRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture. Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory(DRAM) applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor(Fin-FET), Wafer bonded double gate and silicon on nothing(SON) gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/ silicon(PIS) capacitors to the metal/insulator/metal(MIM) capacitors used for today 50 nm technology node and below. In comparing Ta2O5 , HfO2 and Al2 O3 as high-k dielectric for use in DRAM technology, Al2 O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture.
出处 《Semiconductor Photonics and Technology》 CAS 2008年第3期186-191,212,共7页 半导体光子学与技术(英文版)
关键词 半导体 集成技术 材料 技术性能 DRAM multi-gate Fin-FET high-k dieleetric capacitor
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参考文献16

  • 1Faul J W, Henke, D. Transistor challenges A DRAM perspeetive[J]. Nuclear Instruments and Methods in Physics Research Section B, 2005, 237(1-2): 228-234.
  • 2Seo J Y, Lee K L, Lee S Y, et al. Dielectric reliability of stacked Al2 O3- HfO2 MIS capacitors with cylinder type for improving DRAM data retention characteristics[J]. Microelectronics Reliability, 2005, 1 360-1 364.
  • 3Vinet M, Sanborn K. High performance 10nm bonded planar double metal gate CMOS transistors[J]. IEEE-EDL, 2005, 5(5): 25-31.
  • 4Harrison S, MA Dong-sheng. Highly performant double gate MOS-FET realized with SON process[J]. IEDM TD, 2003, 3(2): 449-452.
  • 5Huang X, Ivanov V. Sub-50 nm FinFET[J]. IEDM TD, 1999. 21(2): 67-72.
  • 6Monfray S, Granneman E, Fischer P. SON technological CMOS platform: highly performant devices and SRAM cells [J]. IEDMTD, 2004, 2(3): 635-640.
  • 7Harrison S, Pierreux D, Terhorst H. Highly performant double gate MOS-FET realized with SON process[J]. IEDM TD, 2003, 2(6): 449-456.
  • 8Yu B, Zagwijn P, Arden W. FinFET scaling to 10 nm gate length[J] IEDM TD, 2002, 7(5) : 251-258.
  • 9Sunami H, Asai S. Trends in megabit DRAMs[J]. VLSI Tech. Dig. , 1985, 24(5): 4-12.
  • 10Koyanagi M, Sunami H, Hashimoto N, et al. Novel high density, stacked capacitor MOS RAM[J]. IEDM Tech. Dig., 1978, 1(1): 348-352.

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