摘要
本文利用模拟余量和模拟余差研制出两种流水折叠分级式ADC,提出了两种电路改进结构——有余差转换和无余差转换,并通过动态性能的测试来对比分析两结构的优缺点.无余差转换的ADC+和由其复合构成的ADC的测试表明,性能分别达到2bits@40MSPS ADC+和2+8bits@40MSPS ADC.对于实际制作的ADC电路,具体给出了结构图以及动态性能测试图.
This paper applies the remainder of analogue quantity and the residue of analogue quantity to the implementation of pipelined folding and subranging ADCs. Two improved circuit structures are proposed, one structure makes use of the conversion of residue of analogue quantity, while the other doesn't. Experiments on dynamic performance of two structures are conducted. The test result shows that ACD + built without conversion of residue of analogue quantity can achieve a performance of 2bits@40MSPS ADC+ and 2+8bits@40MSPS ADC. FinaUy ,the structure and dynamic performance test graph are given in detail for practical implementation of ADC circuit.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2008年第8期1651-1654,1659,共5页
Acta Electronica Sinica
基金
国家自然科学基金(No.90407001)
深圳市科技计划项目(No.200512)
关键词
模数转换器
折叠
分级
模拟余差
模拟余量
analog to digital converter (ADC)
folding
subranging
residue of analogue quantity
remainder of analogue quantity