基于FPGA的PWM与定时计数器IP核的设计

Design of PWM and time counter IP core based on FPGA

基于硬核嵌入式CPU中的PWM/定时计数器模块与FPGA的广泛应用,本文提出了一种软件式的PWM/定时计数器数字逻辑电路的设计思想。用硬件描述语言HDL编写总线接口、功能逻辑与外部I/O电路,并描述了硬件驱动程序的设计过程。对其结果进行了软件仿真并定制到NIOSⅡ中进行调试,实验结果证明.该设计具有很好的实际效果。

Based on the widespread application of PWM / timing counter modules and FPGA in the hard core embedded CPU, we propose a software design ideas of PWM / timing counter digitallogic circuit. HDL hardware description language is used to prepare bus interface, logic functions and external I / O circuit, and described the driver of the hardware design process. Have carried on software emulation and debugged in NIOS II to its result, the experimental re- sults show that the design has a good practical results.