集成电路时延关键路径算法及其实现

An Algorithm for Critical Path Extraction and Its Implementation in IC Timing Optimizaton

研究关键路径问题是时延驱动集成电路设计的基础。提出了一种改进的关键路径算法，实现了对任意的有向图提取Ｋ条关键路径。算法速度快，实用性强。

The problem of extracting critical paths is an important consideration of timingdriven IC design. A modified algorithm for critical path extraction is described in the paper, which generates the K most critical paths in terms of their delays for any given directed graph. Experiments indicate its fast speed and high effectiveness. It has been demonstrated that the algorithm can find applications in timing analysis and optimization for high density and high speed IC’s.