应用于SoC的低功耗MPEG-1/2音频解码IP

A Low Power MPEG-1/2 Audio Decoer IP Core

文章设计了一个低功耗、可复用、MPEG-1/2LayⅠ/Ⅱ/Ⅲ音频解码IP核。该IP核主要应用于包含一个CPU的嵌入式多媒体处理系统。该IP核包含了一个Software-Core和一个Hardware-Core,在两者的配合下,可以在非常低的时钟频率下高精度解码MPEG-1/2LayⅠ/Ⅱ/Ⅲ音频码流。在实时解码128kbps/44.1kHz MPEG-1/2LayerⅢ码流时,Hardware-Core工作在5.6448MHz,Software-Core工作在8MHz。文章最后给出另一个该IP在典型SoC系统中的应用。Hardware-Core在CMOS0.18 μ m工艺下,芯片面积为1520 μ m×1280 μ m。

This paper presents a reusable, portable, low cost and low power MPEG-1/2 layer I / Ⅱ / Ⅲ decoder IP core. The IP core consists of software core and hardware core. By the corporation between the two parts, they can real-timely decode MPEG-1/2 layer I / Ⅱ / Ⅲ audio bit stream at a very low clock frequency. And the IP core is a totally full compliance MPEG audio decoder for providing 6.0896×10^-8 RMS level. In the case decoding a random 128 kbps/44.1 kHz MPEG- 1/2 layer I /Ⅱ/Ⅲ real-timely, the hardware-core works at 5.644 8 MHz while software-core works at 8MHz. And its die size is 1520μm×1280μm including on-chip SRAM and ROM.