亚微米BiCMOS电路纵向NPN管的ESD保护研究

Research on ESD Protection Circuit with Vertical NPN Structure in Submicron BiCMOS Technology

文章以0.6μmN外延BiCMOS工艺为基础,研究了纵向NPN管的ESD保护行为,并对不同版图结构的纵向NPN管进行了ESD行为研究。实验表明,由于基区的内在电阻不一样,在该工艺条件下,CEB、CEBE结构比CBE、CBEB结构SNAPBACK效应明显,机器模式下ESD保护能力强。此外,还研究了兼容低压Vz工艺,单级保护NMOS输出管的纵向NPN器件的ESD行为,流片显示采用EB结齐纳击穿的纵向NPN能有效单级保护CMOS的输出级。

The I-V characteristics of vertical NPN under ESD conditions for 0.6μm BiCMOS process are presented. The ESD performance for some kinds of vertical NPN layout techniques is investigated. For 0.6μm BiCMOS process, because of the different internal base resistance, CEB, CEBE structures have better SNAPNACK effect and a high ESD protection efficiency than CBE, CBEB structures. It is also shown that the vertical NPN can effectively protect NMOS transistor in the output buffer by means of a zener transistor and the vertical NPN has no series resistance in the signal path.