基于FPGA的μ子鉴别器读出系统前端电路

Front-end card of muon counter using FPGA chips

介绍了北京谱仪第三代工程(BESIII)中的μ子鉴别器读出系统的前端电路设计,包括系统的结构、各部件的基本功能和工作原理、触发选通逻辑的设计和系统防干扰等关键问题的设计思路和实现方法,以及采用FPGA的实现过程。经过系统检测,前端电路及其组成的数据链全部实现了预期的设计目标。

Development of front-end card of muon counter for the BES Ⅲ （Beijing Spectrometer Ⅲ） project is presented in this paper. The system structure, functions of the components, strobe logic design, anti-jamming and realization with FPGA are introduced. The front-end card and data-chain worked perfectly under the given conditions, and the design goals were achieved.