摘要
文中提出了一种新型锁相频率合成器[1]的设计实现方法。这种锁相频率合成器的各个部件都进行了优化设计,其中鉴相器采用了加入反相器链取出输入信号边沿的结构很好的消除了鉴相死区;电荷泵采用了差分电路结构消除了跳跃现象;压控振荡器采用了电流模驱动延迟环结构得到了优良的性能;尤其是分频器的设计采用了内、外两分频器的结构,通过改变两个分频器的倍频数N和M的值,可以合成多种时钟频率。
The article proposes a method of design and realization in view of the phase-locked frequency synthesizer with the fine performance. Each part of this kind of phase-lock frequency synthesizer has all carried on the optimized design. The phase detector has joined the phase reverser chain to take out the input signal border in order to eliminate the death, area of PD. The charge pump has used the differential circuit structure to eliminate the jump phenomenon. The voltage controlled oscillator has used the structure of current-controlled delay to obtain the fine performance. In particular, the frequency divider has used in and out two frequency-divider structures,Through to change the N and M value which is the multiple frequency, we may synthesize many kinds of clock frequencies.
出处
《微计算机信息》
北大核心
2008年第26期306-307,305,共3页
Control & Automation
基金
教育部科学技术研究重点项目(207007)毫米波介质谐振器天线技术研究
关键词
鉴相器
电荷泵
压控振荡器
锁相环
phase detector
charge pump
voltage controlled oscillator
phase-locked loop
