用于CMOS图像传感器的列并行RSD循环ADC

A column RSD cyclic ADC for CMOS image sensor

设计了一种用于CMOS图像传感器的列并行RSD循环ADC。转换和采样同步进行,速度比传统的循环ADC提高了1倍,适用于高速实时系统的应用。将采样保持,精确乘2和像素信号的FPN噪声消除功能用1个运放和6个电容来实现,大大缩小了面积。采用RSD算法,不但降低了对比较器的精度要求,并且实现了较高的线性度。通过失调反向存储,基本消除运放失调引入的列FPN噪声。该ADC在0.18μm工艺下,实现了10位精度和500KS/s的高转换速度。ADC的DNL=+0.5/-0.5LSB,INL=+0.1/-1.5LSB。

A column paralld RSD cyclic ADC for CMOS image sensor is designed. The ADC converts the data simultaneously with the sampling,which leads to twice speed of the conventional cydic ADC. An amplifier and six capadtors are used for the S/H,muhiply by two and pixel signal FPN noise candlation,which greatly reduces the size. The RSD algorithm reduces the required comparator accuracy,and realizes high linearity. By storing the offset voltage reversely,the column FPN noise introduced by the offset of the amplifier is diminated, The ADC achieves the accuracy of 10 bit and higt conversion rate of 500 KS/s with 0.18 μm process. The DNL and INL of the ADC are ±0.5/-0.5 LSB and ＋0.1/-1.5 LSB respectively.