G比特级通用可逆计数器的CMOS电路设计

The CMOS circuit design of Gbps general Up/Down counter

在数字锁相环中,可逆计数器是组成数字滤波器的关键电路,本文讨论了通用可逆计数器的工作原理,推导出了电路的逻辑表达式,并设计了五位且可扩展的可逆计数器的电路原理图。采用仿真器NC-Verilog进行了功能验证,同时采用CMOS电路实现了整体功能,最后利用Cadence的Spectre给出了该电路在0.18um CMOS工艺下的晶体管级仿真结果,电路最高工作频率可以达到1.25GHz;而利用Synopsys的Design Compiler对规范书写的Verilog模块在相同工艺下进行逻辑综合得到的电路最高频率只能达到800MHz。

In digital PLL, the up/down counter is the critical circuit of digital filter. This paper presented the principle of the general up/down counter, deduced the logic expressions of the circuit, and designed the circuit schematic of the 5 bits up/down counter which can be extended. The counter＇s functions were verified with the simulator NC-Verilog. It was implemented with CMOS circuit, and the transistor-level simulation was presented with the Cadence Spectre in the 0.18um CMOS technology. The highest frequency of this circuit is 1.25GHz. However, the highest frequency of the circuit which was synthesized from the synthesizable Verilog module in the same process is only 800MHz.