高速低功耗CAM核心电路的设计

Design of High-Speed and Low-Power Nuclear Circuit in CAM

设计了一种新型高性能的CAM(content addressable memory)单元.将差分互补电路应用于CAM存储单元的比较电路中,得出差分互补CAM存储单元,并对预充电电路、放大电路进行设计.电路采用0.18μm CMOS标准工艺来实现,在HSPICE的平台下进行仿真.仿真结果表明,对于64×64的差分互补CAM,最快的比较时间为331 ps,最慢比较时间为762 ps,总的功耗为17.8 mW.

A new high-performance content CAM （addressable memory cell） was designed. Complementary differential circuit was used in the comparative circuit of CAM cell to work out complementary-different CAM cell. And then, pre- charge and amplify circuit were also designed. The circuit was completed under the 0.18 um CMOS standard process and simulated with the tool of HSPISE. The following were the outcome of simulation with CAM with a volume of 64 ×64： the fastest comparative time was 331 ps, the slowest comparative time was 762 ps and the power depletion was 17.8 mW.