摘要
高速缓存作为中央处理器(CPU)与主存之间的小规模快速存储器,解决了两者数据处理速度的平衡和匹配问题,有助于提高系统整体性能。多处理器(SMP)支持共享和私有数据的缓存,Cache一致性协议用于维护由于多个处理器共享数据引发的多处理器数据一致性问题。论述了一个适用于64位多核处理器的共享缓存设计,包括如何实现多处理器缓存一致性及其全定制后端实现。
The cache between high speed CPU and low speed system memory solves the speed matching between CPU and system memory which has a direct effect on the performance of microprocessors. Shared cache in SMP（Symmetrical Multi-Processing） support caching of shared and private data. Cache coherency protocol maintains the data coherence in multiprocessors. The paper presents a shared cache design for 64-bit SMP, which contains the implementation of cache coherency and its full custom circuit and layout.
出处
《计算机与数字工程》
2008年第9期148-150,共3页
Computer & Digital Engineering
