AVS环路滤波器的VLSI设计与实现

VLSI Design and Implementation of Loop Filter for AVS

设计并实现了一种适用于AVS高清解码器的环路滤波器。该结构利用将水平边和竖直边相邻块数据分开存储的方法,以及流水线的滤波操作,加快了环路滤波器的处理速度,提高了工作频率。利用片内SRAM部分数据自更新的方法,减少了数据的传输。该VLSI实现采用0.18μm CMOS工艺综合的最高工作频率为167 MHz,电路规模约36 k等效逻辑门(含片内SRAM)。仿真结果显示,设计的环路滤波器能够对AVS高清视频(1 280×720 60帧/s)进行实时的环路滤波。该环路滤波器可用于AVS高清实时解码器芯片中。

VLSI design and implementation of loop filter for AVS high -definition video decoder is presented in this paper. The data which are side by row bound and column bound are stored in different SRAMs to accelerate loop filter processing. The pipeline structure are adopted in calculate unit to improve the frequency. One of SRAM updates part of data from other SRAM to minimize data transfer. The implementation is described in Verilog HDL,simulated with ModelSim and synthesized using 0.18 μm CMOS cells library by Synopsys Design Compiler. The circuit totally costs about 36k logic gates when working frequency is set to 167 MHz. The circuit processes a macro block using 436 cycles. Simulation results show that the implementation can be used in real- time HDTV（1 280× 720 60 f/s） AVS video decoder.