摘要
根据国际半导体技术发展蓝图(international technology roadmap for semiconductor,ITRS),CMOS技术将于2009年进入32nm技术节点.然而,在CMOS逻辑器件从45nm向32nm节点按比例缩小的过程中却遇到了很多难题.为了跨越尺寸缩小所带来的这些障碍,要求把最先进的工艺技术整合到产品制造过程中.文中总结并讨论了可能被引入到32nm节点的新的技术应用,涉及如下几个方面:浸入式光刻的延伸技术、迁移率增强衬底技术、金属栅/高介电常数栅介质( metal/high-k,MHK)栅结构、超浅结(ultra-shallowjunc-tion,USJ)以及其他应变增强工程的方法,包括应力邻近效应(stress proximity effect,SPT)、双重应力衬里技术(dual stress liner ,DSL)、应变记忆技术(stress memorization technique,SMT)、STI和PMD的高深宽比工艺(high aspect ratio process,HARP)、采用选择外延生长(selective epitaxial growth,SEG)的嵌入Si Ge(pFET)和SiC(nFET)源漏技术、中端( middle of line,MOL)和后端工艺(back-end ofline,BEOL)中的金属化以及超低k介质(ultra low-k,ULK)集成等问题.
According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
