一种基于CMOS工艺的新型结构ESD保护电路

A Novel ESD Protection Circuit Based on a CMOS Process

根据全芯片静电放电(ESD)损伤防护理论,设计了一种新型结构保护电路,采用0.6μm标准CMOSp阱工艺进行了新型保护电路的多项目晶圆(MPW)投片验证.通过对同一MPW中的新型结构ESD保护电路和具有同样宽长比的传统栅极接地MOS(GG-nMOS)保护电路的传输线脉冲测试,结果表明在不增加额外工艺步骤的前提下,本文设计的新型结构ESD保护电路芯片面积减少了约22%,静态电流更低,而抗ESD电压提高了近32%.该保护电路通过了5kV的人体模型测试.

A new electrostatic discharge （ESD） protection circuit based on a standard 0.6μm CMOS p-well process is designed according to the whole-chip ESD protection theory and verified by a multi-project wafer （MPW） fabrication. The characteristics of the new ESD protection structure and traditional gate grounded nMOS （GG-nMOS） protection circuit with the same channel ratio of width/ length in the MPW are measured by a transmission line pulse generator system. The results show that the area of the new ESD protection circuit decreases about 30%. Lower static current and an increase in the failure voltage up to 30% are achieved compared to those of a GG-nMOS protection circuit with the same manufacturing process. An ESD failure voltage up to 5kV under human-body mode test conditions is obtained.