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双核处理器性能最优的共享Cache划分 被引量：4

A Performance-oriented Runtime Mechanism for Shared Cache Partition of Dual-core Processor
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摘要 文中使用模拟器模拟的方法,测试IPC-CP对多道程序的吞吐率、加权加速比和公平性的影响.实验结果表明:以IPC最优为目标的Cache划分在三个评估指标中都优于以失效率最优为目标的Cache划分.其中,IPC-CP的吞吐率最高比失效率最优的Cache划分高出54%,平均高出27%. This paper presents the evaluation of IPC-CP on top of a dual-core processor simulator,with 12 multi-programmed workloads,shows that IPC-CP improves performance by up to 54% and on average 27% over UCP.
作者 所光 杨学军
机构地区 国防科技大学计算机学院
出处 《微电子学与计算机》 CSCD 北大核心 2008年第9期28-30,33,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(60621003 60603081) 国家"八六三"计划项目(2007AA12Z147 2007AA01Z102)
关键词 多核处理器 共享CACHE划分 IPC-CP chip multi-processor shared Cache partition IPC-CP
分类号 TP302 [自动化与计算机技术—计算机系统结构]
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参考文献7

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同被引文献18

  • 1林明亮,祝永新.基于SimpleScalar的异构多核仿真器[J].微电子学与计算机,2007,24(7):204-208. 被引量：7
  • 2Fei Sun, Srivath.s Ravi, Anand Raghunathan. Applicationspecific heterogeneous multiprocessor synthesis using extensible processors [ J ]. IEEE Transactions on CAD of Integrated Circuits and Systems, 2006, 25(9) : 1589- 1602.
  • 3Chris Rowen. Engineering the complex SOC fast flexibel design with configurable processors[M]. USA: Prentice Hall, 2005.
  • 4David Butenhof. Programming with POSIX threads[M]. USA: Addison - Wesley, 2003.
  • 5Chen Guobing, Chen Tianzhou, Yan Like. On - chip communication framework design for embedded heterogeneous [D]. Zhejiang: Zhejiang University,2007.
  • 6Seng Lin Shee, Andrea Erdos, Sri Parameswaran. Heterogeneous multiprocessor implementations for JPEG: a case study[J]. CODES ISSS, 2006,11(3) :217-222.
  • 7Wong W, Baer J L. Modified LRU policies for improving second-level cache behavior [J]. HPCA- 6, 2000 : 49-60.
  • 8Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system[EB/OL](2001) [2010-04 -26]. http://www, patentstorm, us/patents/6240489/description, html.
  • 9Renau J. SESC[EB/OL]. [2010-04-26]. fttp:// sesc. sourceforge, net, 2004.
  • 10Chun Liu, Anand Sivasubramaniam, Mahmut Kandemir. Organizing the last line of defense before hit- ting the memory wall for CMPs [C]//Proceedings of the International Symposium on High-Performance Computer Architecture ( HPCA' 004). Washington, DC,USA.. IEEE Computer Society, 2004: 176-185.

引证文献4

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微电子学与计算机
2008年 第9期

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